3-D smart power IC

ABSTRACT

An integrated smart power circuit including a power semiconductor device fabricated on a conducting substrate with a source positioned adjacent the upper surface of the substrate, a control terminal between the upper and lower surfaces, and a drain positioned adjacent the lower surface of the substrate. A high resistance layer is formed on a portion of the upper surface of the substrate, either directly overlying or adjacent to the power device, and doped semiconductor material is positioned on the high resistance layer. Control circuitry is formed in the doped semiconductor material. The high resistance layer can be conveniently formed by growing a layer of AlAs and growing doped layers on the AlAs. The AlAs can be easily oxidized thereafter.

FIELD OF THE INVENTION

[0001] The present invention pertains to smart power ICs and moreparticularly to the fabrication of power semiconductor devices andcontrol circuitry on the same substrate.

BACKGROUND OF THE INVENTION

[0002] Semiconductor power devices and, in particular, GaAs verticalpower devices require conductive substrates so that one of the currentcarrying terminals (e.g. the drain) can be positioned on the reverseside. Control circuitry including field effect transistors (FETs), aregenerally include for controlling the power devices. However, GaAscontrol devices are usually fabricated using a plurality of thinepitaxial layers grown on a semi-insulating substrate. Thus, integrationof the power devices and the control devices on a common substrate isnot normally convenient.

[0003] In the past, integration of power and control devices has beenaccomplished by implanting a P-type well in an N-type substrate. Powerdevices are then fabricated in the conducting substrate and N-channelFETs, or control devices are fabricated in the P-type well. Thesecircuits have poor isolation and there is a tendency to create parasiticjunctions which substantially degrade the operation or requireadditional compensating structure. Also, the implanted wells use largeamounts of substrate, so that the level of integration is very poor.

[0004] Another solution for combining power and control circuits on acommon substrate is to form a large buried gate structure for thevertical power devices. The buried gate structure generally includes ap-type buried layer formed by implant, epitaxial growth etc. A portionof the buried gate structure is then used to isolate the controlcircuitry, which is fabricated above the portion of the buried gatestructure, by including a vertical implant extending from the surface tothe portion of the buried gate structure between the vertical powerdevices and the control devices. In this structure the buried gate andthe vertical implant form a P-type isolation barrier beneath the controldevices and between the control and power devices. This type ofcombination also has poor isolation and there is a tendency to createparasitic junctions which substantially degrade the operation or requireadditional compensating structure. Further, the implanted wells againuse large amounts of substrate, so that the level of integration is verypoor.

[0005] Thus, it would be highly desirable to provide high levelintegration of vertical power devices and control circuitry on a commonsubstrate.

[0006] It is a purpose of the present invention to provide a new andimproved integrated smart power IC.

[0007] It is another purpose of the present invention to provide a newand improved integrated smart power IC with improved isolation.

[0008] It is still another purpose of the present invention to provide anew and improved integrated smart power IC with a higher level ofintegration than prior art circuits and with reduced die size.

[0009] It is a further purpose of the present invention to provide a newand improved integrated smart power IC in which the isolation isrelatively easy and inexpensive to fabricate.

SUMMARY OF THE INVENTION

[0010] The above problems and others are at least partially solved andthe above purposes and others are realized in an integrated smart powercircuit including a power semiconductor device fabricated on aconducting substrate with a first current carrying terminal positionedadjacent the upper surface of the substrate, a control terminalpositioned between the upper and lower surfaces, and a second currentcarrying terminal positioned adjacent the lower surface of thesubstrate. A high resistance layer is formed on a portion of the uppersurface of the substrate, either directly overlying or adjacent to thepower device, and doped semiconductor material is positioned on the highresistance layer. Control circuitry is formed in the doped semiconductormaterial.

[0011] In a specific embodiment, the high resistance layer can beconveniently formed by growing a layer of AlAs and growing doped layerson the AlAs. The AlAs can be easily oxidized thereafter. In anotherembodiment, a layer of low temperature GaAs is formed on the uppersurface of the substrate followed by an AlGaAs buffer layer and a GaAschannel layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Referring to the drawings:

[0013]FIG. 1 is a simplified sectional view of an integrated smart powerIC in accordance with the present invention;

[0014]FIG. 2 is a simplified sectional view of another integrated smartpower IC in accordance with the present invention;

[0015]FIG. 3 is an isometric view illustrating the relationship of powerand control circuits in one embodiment of an integrated smart power ICin accordance with the present invention;

[0016]FIG. 4 is an isometric view illustrating the relationship of powerand control circuits in another embodiment of an integrated smart powerIC in accordance with the present invention; and

[0017]FIG. 5 is a view in top plan of an embodiment similar to theembodiment of FIG. 4.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Turning now to the drawings, FIG. 1 is a simplified sectionalview of an integrated smart power IC 10 in accordance with the presentinvention. In this specific embodiment, integrated smart power IC 10includes a power semiconductor device 11 (e.g. a power JFET) and controlcircuitry 12. Basically, integrated smart power IC 10 is fabricated on asubstrate 15 having a lower or rear surface 16 and an upper or frontsurface 17. Substrate 15 is generally lightly doped (in this instanceN-type conduction) to provide for conduction therethrough, usuallyreferred to as a drift region and may have more heavily doped contactlayers adjacent surfaces 16 and 17. In some instances additionalepitaxial layers may be grown in accordance with specific fabricationtechniques but all such layers are considered and will be referred tohereinafter as substrate 15.

[0019] A conductor 18, usually a metal forming an ohmic contact, isdeposited on surface 16 and serves as one current terminal for powersemiconductor device 11, generally a drain terminal. A current terminal20, generally a source terminal, includes a heavily doped region 21having a metallization layer 22 deposited thereon. Generally, theheavily doped region is formed by implantation or diffusion, dependingupon the materials and process, and the metallization is formed bylift-off or any of the other techniques well known in the semiconductorindustry. In the fabrication process, a trench 25 is etched intosubstrate 15 using standard masking techniques, so that current terminal20 has trench 25 positioned on each side thereof. Here it should benoted that the drawings are not drawn in the correct dimensionalrelationship but are designed for convenience of understanding. Also, itshould be noted that trench 25 may be circular, oval or race-trackshaped, serpentine or any other shape designed to make the area of powersemiconductor device 11 sufficiently large to produce whatever currentis required. The bottom of trench 25 is heavily doped with P+doping 26to form a control or gate terminal which is contacted either directly,as illustrated by metallization layer 27 or at some remote point.Typically, doping 26 is achieved by implant and anneal for activation,after which metallization layers 22 and 27 are provided.

[0020] Control circuitry 12, in this specific embodiment is formedadjacent power semiconductor device 11 and in this embodiment at oneedge of trench 25. A high resistance layer 30 is formed on surface 17 ofsubstrate 15 adjacent trench 25. One or more doped semiconductor layers31 are formed on the surface of high resistance layer 30. A plurality ofcontrol devices, e.g. field effect transistors (FETs) 32 and 33, areformed in doped semiconductor layers 31 using any convenientsemiconductor technique or process. In a typical example, metal gates 34and 35 are formed by some usual patterning process and a source anddrain (e.g. 36,37 and 38, 39, respectively) are formed on either side ofeach gate 34 and 35 by implantation or diffusion. Metallization is thenperformed to connect power semiconductor device 11 and control circuitry12 into integrated smart power IC 10.

[0021] In a preferred embodiment, substrate 15 is formed of galliumarsenide (GaAs) and high resistance layer 30 is formed by depositing orepitaxially growing a layer of aluminum arsenide (AlAs) on surface 17thereof. This can be accomplished relatively easily, since the crystalstructures are relatively well matched. One or more semiconductor layers31 (e.g. GaAs) can then be epitaxially grown on the surface of highresistance layer 30 using well known techniques. Either before or afterthe completion of control circuitry 12, the AlAs is converted to Al₂O₃by low temperature oxidation. Such oxidation will proceed from the edgesof layer 30 laterally if the size of the die is not too large.

[0022] While high resistance layer 30 can be formed using a variety ofdifferent processes, the above described method using AlAs is one of themost convenient. Another embodiment which can be conveniently utilizedis to form a layer of low temperature GaAs on the upper surface of thesubstrate. The formation of low temperature GaAs is well documented andunderstood by those skilled in the semiconductor art. In this specificembodiment, an AlGaAs buffer layer is formed on the low temperature GaAslayer followed by a GaAs channel layer.

[0023] Turning now to FIG. 2, a simplified sectional view is illustratedof another embodiment of an integrated smart power IC 10′ in accordancewith the present invention. Components similar to components in FIG. 1are designated with similar numerals having a prime added to indicatethe different embodiment. In this specific embodiment, integrated smartpower IC 10′ includes a power semiconductor device 11′ (e.g. a powerJFET) and control circuitry 12′. Basically, integrated smart power IC10′ is fabricated on a substrate 15′ having a lower or rear surface 16′and an upper or front surface 17′. Substrate 15′ is generally lightlydoped (in this instance N-type conduction) to provide for conductiontherethrough, usually referred to as a drift region and may have moreheavily doped contact layers adjacent surfaces 16′ and 17′. In someinstances additional epitaxial layers may be grown in accordance withspecific fabrication techniques but all such layers are considered andwill be referred to hereinafter as substrate 15′.

[0024] A conductor 18′, usually a metal forming an ohmic contact, isdeposited on surface 16′ and serves as one current terminal for powersemiconductor device 11′, generally a drain terminal. A current terminal20′, generally a source terminal, includes a heavily doped region orlayer which may be formed by implanting or diffusing into the uppersurface of substrate 15′ or by epitaxially growing a doped layer on thesurface of substrate 15′ (the epitaxial layer being considered a portionof substrate 15′ herein). A control terminal 26′ is formed by providingheavily doped regions 26′ (with P+doping) positioned between lowersurface 16′ and upper surface 17′ of substrate 15′. Regions 26′ can beformed using a variety of processes including implanting, growingepitaxial layers, etc. External connections to current terminal 20′ andcontrol terminal 26′can be made through vias (not shown) or at one ofthe edges of integrated smart power IC 10′. Thus, one or more powersemiconductor devices 11′ are fabricated in substrate 15′with a planarupper surface 17′.

[0025] A high resistance layer 30′ is formed on surface 17′ of substrate15′ and one or more doped semiconductor layers 31′are formed on thesurface of high resistance layer 30′. A plurality of control devices,e.g. field effect transistors (FETs) 32′ and 33′, are formed in dopedsemiconductor layers 31′ using any convenient semiconductor technique orprocess. In a typical example, metal gates 34′ and 35′ are formed bysome usual patterning process and a source and drain (e.g. 36′,37′ and38′, 39′, respectively) are formed on either side of each gate 34′ and35′ by implanting or diffusion. Metallization is then performed toconnect power semiconductor device 11′ and control circuitry 12′ intointegrated smart power IC 10′.

[0026] In a preferred embodiment, substrate 15′ is formed of galliumarsenide (GaAs) and high resistance layer 30′ is formed by depositing orepitaxially growing a layer of aluminum arsenide (AlAs) on surface 17′thereof. This can be accomplished relatively easily, since the crystalstructures are relatively well matched. One or more semiconductor layers31′ (e.g. GaAs) can then be epitaxially grown on the surface of highresistance layer 30′ using well known techniques. Either before or afterthe completion of control circuitry 12′, the AlAs is converted to Al₂O₃by low temperature oxidation. Such oxidation will proceed from the edgesof layer 30′ laterally if the size of the die is not too large.

[0027] Turning now to FIG. 3, an isometric is illustrated showing therelationship of power and control circuits in one embodiment (e.g. theembodiment of FIG. 2) of an integrated smart power IC in accordance withthe present invention. For convenience in understanding, componentswhich are similar to components of FIG. 2 will be designated withsimilar numbers in FIG. 3. Thus, integrated smart power IC 10′ includespower semiconductor device 11′ formed in substrate 15′ and illustratedas a lower layer or block in FIG. 3. High resistance layer 30′ is formedon substrate 15′ and control circuitry 12′ is formed in a layer orlayers overlying high resistance layer 30′. To better understand thefabrication of integrated smart power IC 10′, some specific examples areset forth below.

[0028] In a first specific example and referring to FIG. 3, layer 30′ is800 Å thick with a rectangular area of 100 mils by 100 mils. Generally,the thickness is in a range of 500 Å to 1000 Å thick to provide goodisolation without requiring too much space. A point that should beunderstood is that as layer 30′ is made thicker, there is a tendency tooxidize quicker because of the improved access. With the structure ofFIG. 3 in an oxygen or moisture laden atmosphere, an oxidationtemperature of 440° C. to 450° C. is sufficient to oxidize therectangular mesa in approximately 20 to 30 minutes.

[0029] Turning now to FIGS. 4 and 5, an isometric and top plan view,respectively, are illustrated showing the relationship of power andcontrol circuits in the embodiment illustrated in FIG. 1 of integratedsmart power IC 10 in accordance with the present invention. Forconvenience in understanding, components which are similar to componentsof FIG. 1 will be designated with similar numbers in FIG. 3. Thus,integrated smart power IC 10 includes power semiconductor device 11formed in substrate 15 and illustrated as a lower layer or block in FIG.3. High resistance layer 30 is formed on substrate 15 and controlcircuitry 12 is formed in a layer or layers overlying high resistancelayer 30. Layer 30 and layer or layers 31 can be deposited or grown inblanket form, if desired, and patterned or formed into the mesaillustrated in FIG. 4 by etching. In a specific embodiment an etchsolution of H₃PO₄:H₂O₂:H₂O is used in a 1:8:140 ratio. However, asulfuric etch solution could be used instead, if desired. In thisspecific etch H₃SO₄:H₂O₂:H₂O is used in a 1:1:40 ratio.

[0030] Turning specifically to FIG. 5, the final mesa is illustrated asbeing in a rectangular shape 300 pm by 300 μm, which it has beendetermined is too large to reliably oxidize all of layer 30 in areasonable time. Thus, oxidation vias 40 are etched or otherwise formedat approximately 100 μm intervals. In this specific example, oxidationvias 40 are formed with approximately a 10 μm diameter. It will ofcourse be understood that the diameter is selected to provide the mostreliable oxidation while requiring the least amount of area. In thisexample layer 30 was subjected to approximately 440° C. to 450° C. in anoxygen atmosphere for about 25 to 45 minutes.

[0031] Thus, a new and improved integrated smart power IC is disclosedwith improved isolation, a higher level of integration than prior artcircuits, and with reduced die size. That is, the control circuits canbe fabricated in overlying relationship (three dimensional) to the powerdevices so that chip area is minimized. Further, the new and improvedintegrated smart power IC is fabricated by processes in which isolationis relatively easy and inexpensive to fabricate.

[0032] While we have shown and described specific embodiments of thepresent invention, further modifications and improvements will occur tothose skilled in the art. We desire it to be understood, therefore, thatthis invention is not limited to the particular forms shown and weintend in the appended claims to cover all modifications that do notdepart from the spirit and scope of this invention.

What is claimed is:
 1. An integrated smart power circuit comprising: aconducting substrate having an upper and a lower surface; a powersemiconductor device fabricated on the substrate and including a firstcurrent carrying terminal positioned adjacent the upper surface of thesubstrate, a control terminal, and a second current carrying terminalpositioned adjacent the lower surface of the substrate; a highresistance layer formed on a portion of the upper surface of thesubstrate; doped semiconductor material positioned on the highresistance layer; and control circuitry formed in the dopedsemiconductor material.
 2. An integrated smart power circuit as claimedin claim 1 wherein the substrate includes GaAs.
 3. An integrated smartpower circuit as claimed in claim 1 wherein the power semiconductordevice includes a vertical field effect transistor with the firstcurrent carrying terminal being a source terminal, the control terminalbeing a gate terminal, and the second current carrying terminal being adrain terminal.
 4. An integrated smart power circuit as claimed in claim1 wherein the high resistance layer includes one of a nitride, an oxide,and an amorphous material.
 5. An integrated smart power circuit asclaimed in claim 4 wherein the high resistance layer includes aluminumoxide.
 6. An integrated smart power circuit as claimed in claim 5wherein the aluminum oxide includes a layer of oxidized AlAs depositedon a gallium arsenide substrate.
 7. An integrated smart power circuit asclaimed in claim 4 wherein the high resistance layer includes lowtemperature gallium arsenide deposited on a gallium arsenide substrate.8. An integrated smart power circuit as claimed in claim 1 wherein thehigh resistance layer and the doped semiconductor material with thecontrol circuitry formed therein are positioned in overlyingrelationship to at least a portion of the power semiconductor device. 9.An integrated smart power circuit as claimed in claim 1 wherein thecontrol circuitry includes a plurality of lateral field effecttransistors.
 10. An integrated smart power circuit comprising: aconducting gallium arsenide substrate having an upper and a lowersurface; a vertical power transistor fabricated on the substrate andincluding a first current carrying terminal positioned adjacent theupper surface of the substrate, a gate terminal, and a second currentcarrying terminal positioned adjacent the lower surface of thesubstrate; a high resistance layer formed on a portion of the uppersurface of the substrate, the high resistance layer including one ofaluminum oxide and low temperature gallium arsenide; doped semiconductormaterial positioned on the high resistance layer; and control circuitry,including a plurality of lateral field effect transistors, formed in thedoped semiconductor material.
 11. An integrated smart power circuit asclaimed in claim 10 wherein the aluminum oxide includes a layer ofoxidized AlAs deposited on the gallium arsenide substrate.
 12. Anintegrated smart power circuit as claimed in claim 10 wherein the highresistance layer and the doped semiconductor material with the controlcircuitry formed therein are positioned in overlying relationship to atleast a portion of the power semiconductor device.
 13. A method offabricating an integrated smart power circuit comprising the steps of:providing a conducting substrate with an upper and a lower surface;forming a vertical power semiconductor device on the substrate andpositioning a first current carrying terminal adjacent the upper surfaceof the substrate and a second current carrying terminal adjacent thelower surface of the substrate; forming a high resistance layer on aportion of the upper surface of the substrate; providing dopedsemiconductor material on the high resistance layer; and forming controlcircuitry in the doped semiconductor material.
 14. A method offabricating an integrated smart power circuit as claimed in claim 13wherein the step of forming a vertical power semiconductor deviceincludes positioning gate material between the upper and lower surfacesof the substrate.
 15. A method of fabricating an integrated smart powercircuit as claimed in claim 13 wherein the steps of forming a highresistance layer and providing doped semiconductor material includeepitaxially growing a layer of AlAs on the substrate, epitaxiallygrowing doped semiconductor layers on the AlAs, and oxidizing the AlAseither before or after the step of forming control circuitry in thedoped semiconductor material
 16. A method of fabricating an integratedsmart power circuit as claimed in claim 15 wherein the steps ofepitaxially growing the layer of AlAs on the substrate, epitaxiallygrowing doped semiconductor layers on the AlAs, and oxidizing the AlAsinclude providing oxidation vias through the doped semiconductor layersso as to enhance oxidizing the AlAs.
 17. A method of fabricating anintegrated smart power circuit as claimed in claim 16 wherein the stepof providing oxidation vias includes providing holes with approximatelya 10 μm diameter through the doped semiconductor layers at approximately100 μm intervals.
 18. A method of fabricating an integrated smart powercircuit as claimed in claim 13 wherein the steps of forming a highresistance layer and providing doped semiconductor material includegrowing a low temperature GaAs layer on the substrate, growing an AlGaAsbuffer layer on the low temperature GaAs layer, and growing a GaAs layeron the AlGaAs buffer layer.
 19. A method of fabricating an integratedsmart power circuit as claimed in claim 13 wherein the steps of formingthe high resistance layer includes forming the high resistance layer inoverlying relationship to at least a portion of the vertical powersemiconductor device